Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) or Insulated Gate Field Effect Transistors (IGFETs) are well known in the art. Reference is made to the article "Metal-Oxide-Semiconductor Technology" by William C. Hittinger, published in the August 1973 issue of Scientific American, pages 48 through 57. There are numerous patents, published articles and texts which disclose the theory, methods of fabricating, and circuit devices utilizing MOSFETS or IGFETS. One such text is "MOSFET in Circuit Design" by Robert H. Crawford (Texas Instruments Electronic Series) McGraw Hill, copyrighted 1967 by Texas Instruments Incorporated. Another text is "Electronics: BJTs, FETs, and Microcircuits" by E. James Angelo, Jr., McGraw-Hill Electrical and Electronic Engineering Series, copyrighted by McGraw-Hill 1969.
The MOSFET or IGFET transistor generally comprises a first semiconductor region in which source and drain regions of opposite conductivity type to the region are disposed. A channel region is defined between the source and drain regions. The channel conductivity is variable in accordance with potentials applied to a gate electrode capacitively coupled thereto through an insulating layer disposed on the channel surface. MOS-type transistors are of increasing interest, particularly because of their high input impedance compared with bipolar transistors and also because a large number of such elements may be disposed in a single body of material economically where the intended circuit application requires MOS transistors.
U.S. Pat. No. 3,440,503 granted Apr. 22, 1969 to R. C. Gallagher et al is directed to integrated complementary MOS transistor structures and a method of making the same.
U.S. Pat. No. 3,447,046 granted May 27, 1969 to J. R. Cricchi et al is directed to integrated complementary MOS transistor structures and a method of making same. U.S. Pat. No. 3,447,046 is closely related in subject matter to U.S. Pat. No. 3,440,503. In U.S. Pat. No. 3,447,046, complementary MOS transistors are disclosed utilizing out-diffusion through an epitaxially grown layer to form a region in which one of te transistor elements is disposed, the epitaxially grown layer being opposite in conductivity type to that of the original substrate with an isolation wall, which may also be out-diffused, extending through the epitaxial layer to the substrate. Preferably the out-diffused regions are formed with a slow diffusing impurity such as arsenic.
U.S. Pat. No. 3,450,961 granted June 17, 1969 to J. C. Tsai is directed to semiconductor devices with a region having portions of differing depth and concentration. In U.S. Pat. No. 3,450,961 semiconductor devices, such as MOS transistors, are disclosed with a P type region having portions of different depth and impurity concentration particularly suitable for the base region of bipolar transistors and the channel region of MOS transistors. Such structures are particularly useful in complementary MOS transistor structures. In U.S. Pat. No. 3,450,961 the method disclosed employs the differential effect of different types of insulating layers over a single diffused P type region.
U.S. Pat. No. 3,461,361 granted Aug. 12, 1969 to P. Delivorias is directed to complementary MOS transistor integrated circuits with inversion layer formed by ionic discharge bombardment. U.S. Pat. No. 3,461,361 discloses a method of making a complementary pair of MOS transistors in a single semiconductor substrate body of one conductivity type silicon by first, forming a region of opposite conductivity type in the body, fabricating transistors having opposite type source and drain regions in the regions of different conductivity types, each of these transistors having silicon dioxide gate electrode insulator layers, and, after formation of the silicon dioxide layers, cooling the unit to room temperature in pure dry oxygen. Further, an inversion layer is formed in the MOS transistor by bombarding the gate insulating layer with an ionic discharge, creating acceptor sites in the insulator.
U.S. Pat. No. 3,728,695 granted Apr. 17, 1973 to Dov Frohman-Bentchkowsky is directed to a random-access floating gate MOS memory array. In U.S. Pat. No. 3,728,695 a semiconductor memory array which utilizes floating gate MOS devices as storage elements in the array is disclosed. Each storage element comprises a substrate of a first conductivity type and two spaced apart regions of opposite conductivity types. A floating gate is disposed between said two spaced-apart regions and completely insulated from said substrate by silicon oxide. A second and third gate are disposed above said floating gate and insulated from said floating gate by a layer of silicon-oxide. The space-apart regions of the device, namely the source and drain and the second and third gates are coupled to X and Y lines and to a common ground line or other common lines in the array. By application of appropriate voltages to the lines of the array charge may be selectively placed on and removed from the floating gates of the storage elements in the array, thereby programming the array with "ones" and "zeros". By application of suitable voltages to the array the information stored in the array may be read from the array.
U.S. Pat. No. 3,744,036 granted July 3, 1973 to Dov Frohman-Bentchkowsky is directed to Electrically Programmable read only memory array which employs floating gate metal-oxide-semiconductor (MOS) device as the storage element. The floating gate of the storage element is negatively charged by avalanche injection. A field effect transistor is coupled in series with the storage element to form a single memory cell. A plurality of cells comprise the array. The gate of the field effect transistor is coupled to an X-line of the memory array and one of the other terminals of this transistor, is coupled to a Y-line of the array. The array is electrically programmed by application of information to the X and Y lines of the array.
Memory elements having a floating avalanche-injection metal-oxide-silicon structure have been described by Dov Frohman-Betchkowsky in Electronics, May 10, 1971 at pages 91 through 95.
U.S. Pat. No. 3,774,087 granted to M. Pepper on Nov. 20, 1973 is directed to floating avalanche-injection metal-oxide-silicon memory elements. In U.S. Pat. No. 3,774,087, the structure of the floating avalanche-injection metal-oxide-silicon memory element is modified by having at least one diffused region in the silicon substrate which is isolated from the elements' gate and drain electrodes, which is of opposite conductivity type to the substrate, and which is situated adjacent to the channel region between the gate and drain electrodes. At least one region of the substrate situated adjacent to the channel region is also isolated from the gate and drain electrodes, the buried gate of the floating avalanche-injection metal-oxide-silicon structure partially overlaps these isolated regions and a second gate is provided on the surface of the dielectric layer of the floating avalanche-injection metal-oxide-silicon structure such that it is above and completely overlaps the silicon gate.
U.S. Pat. No. 3,794,862 granted Feb. 26, 1974 to F. B. Jenne is directed to a substrate bias circuit. U.S. Pat. No. 3,794,862 discloses a semiconductor substrate including a field effect charge pump for injecting charge into the substrate and a field effect transistor circuit, connected between the substrate and reference voltage source, responsive to the level of substrate charge for clamping the substrate bias voltage at a desired level. By controlling the gate voltage applied to the field effect transistor circuit and the number and arrangement of transistors in the circuit, the substrate bias voltage can be clamped at a value greater than, equal to, or less than the transistor threshold voltage.
Reference is made to the article entitled "Negative Resistance in FET's: An Aid or An Ailment" by Carl David Todd published in ELECTRONICS, Volume 38, No. 15, July 26, 1965, pages 57 through 61. The Todd publication discusses the phenomenon that variations in internal temperature can produce negative resistance in a silicon field effect transistor (FET) with high pinchoff voltage. The magnitude of negative resistance depends largely on three factors: amount of drain current, how much it changes with temperature, and thermal resistance between internal drain and ambient. For the FET to exhibit a voltage stable negative resistance, its drain current must have a negative temperature coefficient, and that coefficient must be large enough so that drain-current changes with temperature are significant; also, the thermal resistance between drain junction and ambient must be high. For a particular pinchoff voltage, the temperature coefficient of the FET's drain current is the result of two opposing effects, and may be either positive or negative. One effect occurs when the drain voltage is constant; the drain current tends to decrease as temperature increases because the resistivity of the silicon material in the channel has a positive temperature coefficient. The opposing effect is an increase in drain current, caused by variation in the width of the thermally generated depletion layer in the p-n junction between the gate and channel. This variation is caused by a change in pinchoff voltage, which is a result of thermal changes in the gate-to-channel contact potential. The variations in gate-channel junction width tend to increase the drain current as temperature increases.
Semiconductor memory arrays have and are receiving considerable attention in the art. Semiconductor memories have numerous advantages over prior art storage devices, such as magnetic cores, in that they require less power to operate and additionally, a greater amount of information may be stored for a given structural volume of physical memory. Among the prior art semiconductor arrays are included those where information is stored on a capacitor, typically parasitic capacitance, and wherein the information must be refreshed periodically. Also among the prior art semiconductor arrays are the type employing a MOS device having a floating gate as a memory element and the type employing a floating avalanche-injection MOS device. Other prior art memory devices use flip-flops or circuits equivalent thereto for storing information.
In accordance with the invention a multiplication mode bistable MOSFET device is provided wherein the bistable characteristics of the device are substantially, if not solely attributable to the multiplication effect of a relatively high substrate doping, or concentration. The channel length and gate oxide thickness are respectively of secondary or little concern in providing the bistable characteristic. The term multiplication effect is a recognized phenomenon in the art. Multiplication effect as applied to PN junction diodes may be briefly defined as follows:
The theory of Avalanche Multiplication is set forth in the text "Physical Electronics and Circuit Model of Transistors" (Semiconductor Electronics Committee, Volume 2) by Paul E. Gray et al, copyright 1964 by John Wiley Inc. The following excerpt is taken from pages 65 and 66 of the Gray et al text.